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0.35m 16-BIT 44.1KHZ SIGMA-DELTA STEREO DAC
BW0405XA
GENERAL DESCRIPTION
This product is SD Digital-To-Analog Converter for digital audio System (CDP). The product contains Serial-toParallel Converter and Compensation Filter, Digital Volume Attenuator by the MICOM Interface, De-Emphasis Filter, FIR filter, Sinc Filter, digital sigma-delta modulator, analog postfilter, AIF (Anti-Image-Filter). The normal input and output channels provides 90dB SNR (Signal to Noise Ratio) over in band (20kHz). The product employs the 1bit 4th-order sigma-delta architecture with 16bit resolution, over sampling of 64X. And analog postfilter with low clock sensitivity and linear phase, filters the shaping-nosie and outputs analog voltage with high resolution. An on-chip reference voltage is included to allow single supply operations.
FEATURES
-- 16bit SD Digital-To-Analog Converter -- On-Chip Analog Postfilter -- Filtered Line-Level Outputs, Linear Phase Filtering -- On-Chip Voltage Reference -- 90dB SNR -- Sampling Rate 44.1kHz -- Input Rate 1Fs or 2Fs by Normal Mode/Double Mode Selection -- Zero Input Detection Mute -- On-Chip Compensation Filter -- Input Volume Attenuator by the MICOM Interface -- On-Chip De-Emphasis Filter -- On-Chip 4 times oversampling Digital Filter -- Low Clock Jitter Sensitivity -- Single 3.3V~2.5V Power Supply
APPLICATIONS
CD Player, Portable CD Player, CD-ROM, Video-CD, Mini-Disk, DVD etc
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BW0405XA
0.35m 16-BIT 44.1KHZ SIGMA-DELTA STEREO DAC
FUNCTIONAL BLOCK DIAGRAM
VDDD VSSD
VDDA VSSA
SDATA BCK LRCK
S/P Converter & Attenuator
Compensation Filter & De-emphsis & FIR Filter
Sinc Filter & Sigma-Delta Modulator
DAC & Analog Postfilter
AOUTL Anti-Imaging Filter AOUTR
MICOM Interface
Timing Generation
Voltage Reference
VREF VHALF IREF
M C L K
MM DL AD T A
TPMBR SDU I S EL T S T L E TB LO N P
MDD S NE C E K M
S E R R O R B
S D I A G
O F S 6 4
O D S L
O D S R
I F S 6 4
I A D S L
I A D S R
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0.35m 16-BIT 44.1KHZ SIGMA-DELTA STEREO DAC
BW0405XA
EMBEDDED CORE BLOCK DIAGRAM
External Inputs 4 M U X MSCK BCK LRCK SDATA V S S D V D D D V D D A V S S A External AOUTL AOUTR VHALF VREF DEEM DN MUTEL PDL RSTB MCLK MLD MDATA BISTONP TSEL IFS64 IADSL IADSR
4 MUX_SEL
4
Audio Processor (DSP)
5
BW0405XA
IREF SDIAG SERRORB OFS64 ODSL ODSR
3
VSSD
5
These are test pins for internal blocks of the core. So you don't need the internal test mode. Make the test control pins disable ('L') state and Output and bidirectional pins leave foalting.
EMBEDDED CORE USER GUIDE
-- Digital serial data input and clock input refer to digital input format. -- Digital control pins inform refer to pin description. -- Micom I/F pin inform refer to micom interface. -- External application of analog output pins refer to application circuit. -- If you want to test only embedded analog core block (Sigma-Delta DAC), you can do it just adding the 4 pins to supply digital serial input data (LRCK, BCK, SDATA, MSCK) and MUX block. -- Analog power(VDDA,VSSA) and digital power(VDDD, VSSD) should be seperated. -- Two pads should be dedicated to analog power(VDDA, VSSA) -- If you need not use test mode for the testability of internal core block, you make internal core block test pins disable state. (Test Input pins are 'L' state and Test output, bidirection pins leave floating)
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BW0405XA
0.35m 16-BIT 44.1KHZ SIGMA-DELTA STEREO DAC
CORE PIN DESCRIPTION
Symbol Power Supply Pins VDDD VSSD VDDA VSSA Digital Pins MSCK BCK LRCK SDATA MCLK MLD MDATA DEEM DN MUTEL PDL RSTB Analog Pins AOUTL AOUTR VHALF VREF BISTONP TSEL IFS64 IADSL IADSR SDIAG SERRORB OFS64 ODSL ODSR IREF AO AO AO AO DI DI DI DI DI DO DO DO DO DO AB poa_bb poa_bb poar50_bb poar50_bb picc_bb picc_bb picc_bb picc_bb picc_bb pot2_bb pot2_bb pot2_bb pot2_bb pot2_bb poa_bb Analog Output for L-CH Analog Output for R-CH Reference Voltage Output for Bypass Reference Voltage Output for Bypass Memory Bist Test Mode. "H" enabled Test pin for Analog Postfilter Input Selection 64X Sampling Clock Input for Analog Postfilter (When TSEL=H) Inputs for Analog Postfilter of L-CH (When TSEL=H) Inputs for Analog Postfilter of R-CH (When TSEL=H) Test Output pin for embeded memory BIST (BIST_ON="H") Test Output Pin for Embeded memory BIST (BIST_ON="H") 64X Sampling Clock output for Digital sigma-delta Modulator L-CH Output for Digital sigma-delta Modulator. R-CH Output for Digital sigma-delta Modulator. Test Pin for Analog Supply Current DI DI DI DI DI DI DI DI DI DI DI DI picc_bb picc_bb picc_bb picc_bb picc_bb picc_bb picc_bb picc_bb picc_bb picc_bb picc_bb picc_bb Master Clock Input. 384Fs Clock Bit Clock Input. (32Fs or 64Fs) Sample Rate Clock Input. (Fs or 2Fs) Serial Digital Input Micom Interface Clock Input Micom Interface Command load Input (When low,load) Micom Interface Command Data Input De-Emphasis On/Off. "H" is enabled. "L" is disabled. Input Rate Select. High is Double(2Fs) Mode, Low is Normal(Fs) Mode. Analog Output Mute. "L" enabled Power Down. "L" enabled Reset Input. "L" Enabled DP DG AP AG vdd3t_bb vsst_bb vdd3t_bb vsst_bb Digital Supply Digital Ground Analog Supply Analog Ground I/O Type I/O Pad Description
Core Internal Block Test Pins
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0.35m 16-BIT 44.1KHZ SIGMA-DELTA STEREO DAC
BW0405XA
I/O Type Abbr. -- AI: Analog Input -- DI: Digital Input -- AO: Analog Output -- DO: Digital Output -- AB: Analog Bidirectional -- DB: Digital Bidirectional -- AP: Analog Power -- DP: Digital Power -- AG: Analog Ground -- DG: Digital Ground
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BW0405XA
0.35m 16-BIT 44.1KHZ SIGMA-DELTA STEREO DAC
CORE CONFIGURTION
MSCK BCK LRCK SDATA MCLK MLD MDATA DEEM DN MUTEL PDL RSTB BISTONP TSEL IFS64 IADSL IADSR
AOUTL AOUTR VHALF VREF
BW0405XA
Used Power: (VDDD VSSD VDDA VSSA)
IREF SDIAG SERRORB OFS64 ODSL ODSR
ABSOLUTE MAXIMUM RATINGS
Characteristics Supply Voltage Voltage on Any Digital Pin Storage Temperature Range Symbol VDDD,VDDA Vin Tstg Values -0.15 ~ 3.8 VSS-0.15 to VDD+0.15 -45 to +125 Unit V V C
RECOMMENDED OPERATING CONDITIONS
Charateristics Supply Voltage Operating Temp. SYMBOL VDDD VDDA Topr MIN 2.3 0 TYP 2.5 25 MAX 3.6 70 UNITS V C
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0.35m 16-BIT 44.1KHZ SIGMA-DELTA STEREO DAC
BW0405XA
ELECTRICAL CHARACTERISTICS
(VDDD,VDDA=2.5V, Temp=25C, Fs=44.1kHz, Signal Frequency=20-20kHz, Cload of AoutL, AoutR=10pF) Parameter Resolution SNR THD
<1>
Min 80
Typ 16 90 0.005
Max
Units bits dB
<2> <3>
0.01
% dB dB V
SND(THD+Noise) Dynamic Range
76 85
80 90 0.5 x VDDA 0.1 0.75 x VDDA 0.5
<4>
Reference Voltage Ouput Frequency Responce Analog Output Voltage Range Load Impedance Digital Filter Pass Band Ripple Stop Band Attenuation Pass Band Power Supply Analog Current Digital Current Power Dissipation Power Down Current
NOTES: 1. 1kHz 0dB Sinewave Input, EIAJ 2. 1kHz -3dB Sinewave Input 3. 1kHz 0dB Sinewave Input, (Not EIAJ) 4. 1kHz -60dB Sinewve Input, and then measured data + 60dB
dB Vpp
10k 0.0072 62.7 0.45 2 5 17.5 0.1 3 6 22.5 1
dB dB Fs mA mA mW mA
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BW0405XA
0.35m 16-BIT 44.1KHZ SIGMA-DELTA STEREO DAC
AC TIMING CHARACTERISTICS
(VDDD=2.5V, VSSD=0V, Temp=25C) Characteristics MSCK Frequency BCK Frequency (Normal/Doube Mode) MSCK Rising and LRCK Edge Dealay MSCK Risng and LRCK Edge Setup Time BCK Rising and LRCK Edge Dealay BCK Risng and LRCK Edge Setup Time SDATA and BCK Rising Setup Time BCK Ring and SDATA Hold Time Symbol Fmck Fbck Tmld Tmlst Tbld Tblst Tsbst Tbsht 10 10 10 10 10 10 Min - Typ 16.9344 1.4112 / 2.8224 - - - - - - Max - - - - - - - - Unit MHz MHz ns ns ns ns ns ns
MSCK 0.5 VDDD 1/Fmck
BCK 0.5 VDDD 1/Fbck
LRCK Tmld MSCK Tmlst
0.5 VDDD
0.5 VDDD
LRCK Tbld BCK Tsbst SDATA Tbsht Tblst
0.5 VDDD
0.5 VDDD
0.5 VDDD
Figure 1. Timing Chart
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0.35m 16-BIT 44.1KHZ SIGMA-DELTA STEREO DAC
BW0405XA
CLOCK INPUT AND SERIAL INPUT DATA INFORM (FS=44.1KHZ)
DN is normal and double mode selection control pin. Refer to the following table for clock input inform. Table 1. Input Clock Informs Normal Mode (DN='Low') LRCK MSCK BCK 44.1kHz 16.9344MHz 1.4112MHz Double Mode (DN='High') 88.2kHz 16.9344MHz 2.8224MHz
Serial input data (SDATA) is MSB fisrt at falling edge triggered of BCK.
BCK LRCK
...
R-CH DATA
...
L-CH DATA
SDATA
...
MSB
MSB-1 MSB-2
...
LSB+2 LSB+1
LSB
MSB
MSB-1 MSB-2
...
LSB+2 LSB+1
LSB
...
Figure 2. Digital Input Data Format
MICOM INTERFACE (DIGITAL ATTENUATION)
This product can do the function of digital attenuation whenever it receives thd MDATA, MLD, MCLK signals form the MICOM. When the 14-bit serial data is applied to the MDATA, MCLK, MLD in the form of Fig3, according to the data digital attenuation is accomplished. The lower eight LSBs should be 5D(LSB First Format-Hex) and according to the upper 6 bits(LSB First Format-Bin) the attenuation level can be adjusted. (see Table1) When RSTB is low state the latch circuitry for setting the attenuation level becomes reset and the attenuation level is 0dB. At this instance, because the digital filter circuit gets to stop operation the act of attenuation is impossible. In addition, whenever MDATA is not carried, MCLK must be 'HIGH' state. In case of no attenuation fuction needed, MDATA should be 'L', MCLK and MLD should be 'H.
MCLK LSB MDATA Don't Care M0 M1 M2 M3 M4 M5 D(Hex) 5(Hex) MSB Don't Care
MLD Over 550ns needed
Figure 3. MICOM Interface Timing Chart
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BW0405XA
0.35m 16-BIT 44.1KHZ SIGMA-DELTA STEREO DAC
Table 2. Digital Attenuation Level MDATA MSB LSB M5 M4 M3 M2 M1 M0 (h h b b b b b b) 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 -0.28 -0.42 -0.56 -0.71 -0.86 -1.01 -1.16 -1.32 -1.48 -1.64 -1.80 -1.97 -2.14 -2.32 -2.50 -2.68 -2.87 -3.06 -3.25 -3.45 -3.66 -3.87 -4.08 -4.30 -4.53 -4.76 -5.00 -5.24 -5.49 -5.75 -6.02 Attenuation Level (dB) MDATA MSB LSB M5 M4 M3 M2 M1 M0 (h h b b b b b b) 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 -6.30 -6.58 -6.88 -7.18 -7.50 -7.82 -8.16 -8.52 -8.89 -9.28 -9.68 -10.10 -10.55 -11.02 -11.51 -12.04 -12.60 -13.20 -13.84 -14.54 -15.30 -16.12 -17.04 -18.06 -19.22 -20.56 -22.14 -24.08 -26.58 -30.10 -36.12 - Attenuation Level (dB)
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0.35m 16-BIT 44.1KHZ SIGMA-DELTA STEREO DAC
BW0405XA
FUNCTIONAL DESCRIPTION
MCLK MDATA MLD
DEEM DN
MUTEL
SDATA BCK LRCK
1Fs/2Fs 16bits
S/P Converter & Attenuator
Compensation Filter & De-emphasis/ FIR Filter
4Fs/8Fs 16bits
Sinc Filter & Modulator
64Fs 1bit
4bit DAC & SC-Postfilter
Anti-Image Filter
AoutL AoutR
Figure 4. Funtional Block Diagram Fig4 is the 1bit 4th order sigma-delta DAC block daigram. S/P Converter converts serial 16bit input data to parallel 16bit data. Digital input data is attenuated by MICOM interface pin control. Compensation Filter compensates gain droop in Passband by Sinc Filter and Sigma-Dellta Modulator Signal Transfer Function. De-emphasis Block deemphasizes pre-emphasised input data to emphssize high frequency in audible band. FIR Filter perfroms 4X interpolation. And it outputs 4Fs(DN='Low') rate data or 8Fs(DN='High') rate data by variabled input data rate. It also removes the images of the input signal that are present at multiples of the input sample frequency. And Sinc filter makes the constant 64Fs rate data by 16 times or 8 times upsampling FIR Filter output data according to DN(Double/Normal Mode) Pin Selection. This operation intorduces a sinc function responce on the resulting frequency spectrum, which greatly attenuates the energy of images at the multifules of 4Fs(or 8Fs). Digital sigma-delta modulator of bit-stream type has the IFL (Inverse-Follower-Leader) topology, and it performs a noise-shaping function. The modulator shapes the quantization noise by suppressing its in-band component and pushes the noise energy of outside the band-of-interest without deteriorating the audio input signal. The 64 times oversampled 1-bit PDM outputs from the modulator drives a analog postfilter. The analog postfilter comprises SC-postfilter, anti-imaging filter. The SC-postfilter removes the quantization noise shaped to out-of-band by digital sigma-delta modulator. This analog filter has the good clock jitter characteristc and very linear characteristic. And following the CTF(continuous time filter) removes the sampling images and makes the high resolution analog output.
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BW0405XA
0.35m 16-BIT 44.1KHZ SIGMA-DELTA STEREO DAC
APPLICATION CIRCUIT
VDDA
+
0.1uF
+
10uF
Analog Ground Plane
VSSA
VSSA
VDDD
+
0.1uF
+
10uF
VSSD
VSSD
Digital Ground Plane
Figure 5. Bypass Capacitor for Power Supply Pins
VHALF
+
0.1uF
+
10uF
VSSA
VREF
+
0.1uF
+
10uF
VSSA
Figure 6. Bypass Capacitors for Reference Pins
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0.35m 16-BIT 44.1KHZ SIGMA-DELTA STEREO DAC
BW0405XA
Analog pins and digital pins must be seperated, Analog pins should be located on the analog ground plane and digital pins should be located on the digital ground plane. Analog ground and digital ground connection is recommended to only one path through ferrite bead like Fig5. Supply bypass capacitors should be located as close as possible to chip. Small bypass capacitor (0.1uF) should be positioned first to chip than large bypass capacitor (10uF). Reference (VHALF, VREF) bypass capacitors (Fig6) should be located as close as possible to chip.
AOUTL
+ 1uF 100k
L-CH Output
AOUTR
+ 1uF 100k
R-CH Output
Figure 7. Ananlog output application FIg7 is simple high pass filter circuit for analog output. It performs ac-coupling for analog output signal from analog common level to analog ground. Recommended component values are 1uF and 100k. User Guide -- This analog Core Verilog behavioral-modeling will be supplied.
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BW0405XA
0.35m 16-BIT 44.1KHZ SIGMA-DELTA STEREO DAC
FEEDBACK REQUEST
Sigma-Delta DAC Specification We appreciate your interest in our products. If you have further questions, please specify in the attached form. Thank you very much. Parameter supply voltage Max master clock frequency Operating temperature Sampling Frequency Dynamic range Total harmonic distortion Signal-to-noise ratio Input format resolution (Serial/Parallel interface) Channel Power dissipation Full scale output voltage range Group delay Phase linearity deviation for passband region Peak-to-peak frequency response ripple for passband region Mono Min Typ Max Unit V Hz C Hz dB dB dB Bit Stereo mW Vpp sec - (Deg) dB Remarks
-- Could you explain external/internal pin configurations as required? -- Specially requested function list:
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